? semiconductor components industries, llc, 2010 october, 2010 ? rev. 4 1 publication order number: esd11b5.0s/d esd11b5.0st5g transient voltage suppressors micro ? packaged diodes for esd protection the esd11b series is designed to protect voltage sensitive components from esd. excellent clamping capability, low leakage, and fast response time provide best in class protection on designs that are exposed to esd. because of its small size, it is suited for use in cellular phones, mp3 players, digital cameras and many other portable applications where board space comes at a premium. specification features ? low capacitance 12 pf ? low clamping voltage ? small body outline dimensions: 0.60 mm x 0.30 mm ? low body height: 0.3 mm ? stand ? off voltage: 5.0 v ? low leakage ? response time is < 1 ns ? iec61000 ? 4 ? 2 level 4 esd protection ? iec61000 ? 4 ? 4 level 4 eft protection ? these devices are pb ? free, halogen free/bfr free and are rohs compliant mechanical characteristics mounting position: any qualified max reflow temperature: 260 c device meets msl 1 requirements maximum ratings rating symbol value unit iec 61000 ? 4 ? 2 (esd) contact air 15 15 kv total power dissipation on fr ? 5 board (note 1) @ t a = 25 c thermal resistance, junction ? to ? ambient p d r ja 250 400 mw c/w junction and storage temperature range t j , t stg ? 40 to +125 c lead solder temperature ? maximum (10 second duration) t l 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. 1. fr ? 5 = 1.0 x 0.75 x 0.62 in. see application note and8308/d for further description of survivability specs. device package shipping ? ordering information ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d. http://onsemi.com esd11b5.0st5g dsn2 (pb ? free) 5000/tape & reel dsn2 case 152aa marking diagram pin 1 xxxx = specific device code yyy = year code xxxx yyy
bi ? directional tvs i pp i pp v i i r i t i t i r v rwm v c v br v rwm v c v br esd11b5.0st5g http://onsemi.com 2 electrical characteristics (t a = 25 c unless otherwise noted) symbol parameter i pp maximum reverse peak pulse current v c clamping voltage @ i pp v rwm working peak reverse voltage i r maximum reverse leakage current @ v rwm v br breakdown voltage @ i t i t test current *see application note and8308/d for detailed explanations of datasheet parameters. electrical characteristics (t a = 25 c unless otherwise noted) device device marking v rwm (v) i r ( a) @ v rwm v br (v) @ i t (note 2) i t c (pf) v c (v) @ i pp = 1 a v c max max min ma typ max max (note 3) per iec61000 ? 4 ? 2 (note 4) esd11b5.0st5g 11b5 5.0 1.0 5.8 1.0 12 13.5 10 figures 1 and 2 see below 2. v br is measured with a pulse test current i t at an ambient temperature of 25 c. 3. surge current waveforms per figure 5. 4. for test procedure see figures 3 and 4 and application note and8307/d. figure 1. esd clamping voltage screenshot positive 8 kv contact per iec61000 ? 4 ? 2 figure 2. esd clamping voltage screenshot negative 8 kv contact per iec61000 ? 4 ? 2
esd11b5.0st5g http://onsemi.com 3 iec 61000 ? 4 ? 2 spec. level test voltage (kv) first peak current (a) current at 30 ns (a) current at 60 ns (a) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 i peak 90% 10% iec61000 ? 4 ? 2 waveform 100% i @ 30 ns i @ 60 ns t p = 0.7 ns to 1 ns figure 3. iec61000 ? 4 ? 2 spec 50 50 cable tvs oscilloscope esd gun figure 4. diagram of esd test setup the following is taken from application note and8308/d ? interpretation of datasheet parameters for esd devices. esd voltage clamping for sensitive circuit elements it is important to limit the voltage that an ic will be exposed to during an esd event to as low a voltage as possible. the esd clamping voltage is the voltage drop across the esd protection diode during an esd event per the iec61000 ? 4 ? 2 waveform. since the iec61000 ? 4 ? 2 was written as a pass/fail spec for larger systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. on semiconductor has developed a way to examine the entire voltage waveform across the esd protection diode over the time domain of an esd pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all esd protection diodes. for more information on how on semiconductor creates these screenshots and how to interpret them please refer to and8307/d. figure 5. 8 x 20 s pulse waveform 100 90 80 70 60 50 40 30 20 10 0 020406080 t, time ( s) % of peak pulse current t p t r pulse width (t p ) is defined as that point where the peak current decay = 8 s peak value i rsm @ 8 s half value i rsm /2 @ 20 s
esd11b5.0st5g http://onsemi.com 4 the following is taken from application note and8398/d ? board level application note for 0201 dsn2 package. printed circuit board solder pad design based on results of board mount testing, on semiconductor?s recommended mounting pads and solder mask opening are shown in figure 6. maximum acceptable pcb mounting pads and solder mask opening are shown in figure 7. figure 6. recommended mounting pattern figure 7. maximum recommended mounting solder mask two types of pcb solder mask openings commonly used for surface mount leadless style packages are: 1. non solder masked defined (nsmd) 2. solder masked defined (smd) the solder mask is pulled away from the solderable metallization for nsmd pads, while the solder mask overlaps the edge of the metallization for smd pads as shown in figure 8. for smd pads, the solder mask restricts the flow of solder paste on the top of the metallization and prevents the solder from flowing down the side of the metal pad. this is different from the nsmd configuration where the solder flows both across the top and down the sides of the pcb metallization. nsmd smd figure 8. comparison of nsmd vs. smd pads solder mask openings solder mask overlay solderable pcb typically, nsmd pads are preferred over smd pads. it is easier to define and control the location and size of copper pad verses the solder mask opening. this is because the copper etch process capability has a tighter tolerance than that of the solder mask process. nsmd pads also allow for easier visual inspection of the solder fillet. many pcb designs include a solder mask web between mounting pads to prevent solder bridging. for this package, testing has shown that the solder mask web can cause package tilting during the board mount process. thus, a solder mask web is not recommended. pcb solderable metallization there are currently three common solderable coatings which are used for pcb surface mount devices- osp, eniau, and hasl. the first coating consists of an organic solderability protectant (osp) applied over the bare copper features. osp coating assists in reducing oxidation in order to preserve the copper metallization for soldering. it allows for multiple passes through reflow ovens without degradation of solderability. the osp coating is dissolved by the flux when solder paste is applied to the metal features. coating thickness recommended by osp manufacturers is between 0.25 and 0.35 microns. the second coating is plated electroless nickel/immersion gold over the copper pad. the thickness of the electroless nickel layer is determined by the allowable internal material stresses and the temperature excursions the board will be subjected to throughout its lifetime. even though the gold metallization is typically a self-limiting process, the thickness should be at least 0.05 m thick, but not consist of more than 5% of the overall solder volume. excessive gold in the solder joint can create gold embrittlement. this may affect the reliability of the joint. the third is a tin-lead coating, commonly called hot air solder level (hasl). this type of pcb pad finish is not recommended for this type packages. the major issue is the inability to consistently control the amount of solder coating applied to each pad. this results in dome-shaped pads of various heights. as the industry moves to finer and finer pitch, solder bridging between mounting pads becomes a common problem when using this coating.
esd11b5.0st5g http://onsemi.com 5 it is imperative that the coating is conformal, uniform, and free of impurities to insure a consistent mounting process. due to the package?s extremely small size, we only recommend the use of the electroless nickel/ immersion gold metallization over the copper pads. pcb circuit trace width the width of the pcb circuit trace plays an important role in the reduction of component tilting when the solder is reflowed. a solderable circuit trace allows the solder to wick or run down the trace, reducing the overall thickness of the solder on the pcb and under the component. due to the small nature of the solder pad and component, the solder on the pcb will tend to form a bump causing the component to slide down the side of that solder bump resulting in a tilted component on the pcb. allowing the solder to wick or run down the pcb circuit trace, will reduce the solder thickness and in turn prevent the solder from forming a ball on the pcb pad. this was observed during on semiconductor board mounting evaluations. the best results to prevent tilting used a pcb circuit trace equal to the width of the mounting pad. the length of the solder wicking or run out is controlled by the solder mask opening. solder type solder pastes such as cookson electronics? ws3060 with a type 4 or smaller sphere size are recommended. ws3060 has a water -soluble flux for cleaning. cookson electronics? pnc0106a can be used if a no-clean flux is preferred. solder stencil screening stencil screening of the solder paste onto the pcb is commonly used in the industry. the recommended stencil thickness for this part is 0.1 mm (0.004 in). the sidewalls of the stencil openings should be tapered approximately five degrees along with an electro-polish finish to aid in the release of the paste when the stencil is removed from the pcb. see figure 9 for the recommended stencil opening size and pitch shown on the recommended pcb mounting pads and solder mask opening from figure 6. figure 9. recommended stencil pattern. a second stencil option is shown in figure 10 . this option increases the amount of solder paste applied to the pcb through the stencil. this second option increases the stencil opening size and pitch. the pcb mounting pads and solder mask opening on the board do not change from the recommendations in figure 6. figure 10. maximum stencil pattern note: if the maximum stencil opening option from figure 10 is used, tilt may occur on some of the packages. this was evident in the board mounting study we conducted. the stencil with the largest openings may improve solder release from the stencil along with slightly increasing the package shear strength. package placement due to the small package size and because the pads are on the underside of the package, an automated pick and place procedure with magnification is recommended. a dual image optical system where the underside of the package can be aligned to the pcb should be used. pick and place equipment with a standard tolerance of +/- 0.05 mm (0.002 in) or better is recommended. the package self aligns during the reflow process due to the surface tension of the solder.
esd11b5.0st5g http://onsemi.com 6 package dimensions dsn2, 0.6x0.3, 0.4p, (0201) case 152aa ? 01 issue o notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. a b e d bottom view b e 2x 0.05 b a c l 2x 2x 0.06 c top view 2x 0.06 c 2x a a1 0.05 c 0.05 c c seating plane side view dim min max millimeters a 0.24 0.30 a1 0.00 0.01 b 0.22 0.28 d 0.30 bsc e 0.60 bsc e 0.40 bsc l 0.12 0.18 mounting footprint* dimensions: millimeters 0.75 0.28 0.30 0.28 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. 2 1 xxxx yyy jan xxxx y09 year code device code feb mar sep dec jun oct nov indicates aug 2009 (example) cathode band month coding see application note and8398/d for more mounting details on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. esd11b5.0s/d publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
|
